Providing SystemVerilog testing harness for a standardized testing language

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United States of America Patent

PATENT NO 8799864
APP PUB NO 20130067437A1
SERIAL NO

13614877

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Abstract

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A method and apparatus to enable SystemVerilog based tools to compile, debug, and execute a standardized testing language based test bench. The testing harness comprises, in one embodiment, a translator to map TTCN-3 language to a SystemVerilog test bench, a Verilog syntax compiler and simulator database including the mapped TTCN-3 language data, and a run time system using the SystemVerilog test bench with the database including the mapped TTCN-3 language data.

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Patent Owner(s)

Patent OwnerAddress
SYNOPSYS INC690 EAST MIDDLEFIELD ROAD MOUNTAIN VIEW CA 94043

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Junjie Shanghai, CN 25 116
Ji, Xiangdong Hefei, CN 2 9

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