Packet processing in a parallel processing environment

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United States of America Patent

PATENT NO 9787612
SERIAL NO

13487361

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Abstract

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Processing packets in a system that includes a plurality of interconnected processing cores is described. The processing includes receiving packets into one or more queues, associating at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate, mapping a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and at least one rate associated with a node not in the set, and processing the packets in the mapped processor cores according to the hierarchy.

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Patent Owner(s)

Patent OwnerAddress
EZCHIP SEMICONDUCTOR LTD1 HATAMAR STREET YOKNEAM 2069200

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aggarwal, Vijay Marlborough, US 9 485
Steele, Kenneth M Waltham, US 12 273

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