Etch stop layer for memory cell reliability improvement

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8658496
APP PUB NO 20130078795A1
SERIAL NO

13617291

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Abstract

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A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.

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Patent Owner(s)

Patent OwnerAddress
MONTEREY RESEARCH LLC3945 FREEDOM CIRCLE SUITE 900 SANTA CLARA CA 95054

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Kuo-Tung Saratoga, US 118 2735
Hui, Angela Fremont, US 52 851
Kinoshita, Hiroyuki San Jose, US 185 2398
Ngo, Minh Van Fremont, US 269 3858
Ogawa, Hiroyuki Sunnyvale, US 294 5374
Thio, Hsiao-Han Santa Clara, US 10 39

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