Fast condition code generation for arithmetic logic unit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 16, 2014
Grant Date -
Mar 28, 2013
app pub date -
Nov 14, 2011
filing date -
Sep 28, 2011
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully