Fast condition code generation for arithmetic logic unit
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United States of America Patent
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Jun 24, 2014
Grant Date -
Mar 28, 2013
app pub date -
Sep 28, 2011
filing date -
Sep 28, 2011
priority date (Note) -
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Abstract
In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify an arithmetic operation specified in the instruction, and execution logic configured to receive operands specified by the instruction. The execution logic includes a primary logic path configured to perform the arithmetic operation on such operands and a secondary parallel logic path configured to output metadata associated with the result of the arithmetic operation.
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