Strapped dual-gate VDMOS device

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8643067
SERIAL NO

13249529

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Abstract

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Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.

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Patent Owner(s)

Patent OwnerAddress
MAXIM INTEGRATED PRODUCTS INC160 RIO ROBLES DR SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Alberhasky, Scott J Portland, US 4 20
Hart, David E Cornelius, US 2 5
Uppili, Sudarsan Portland, US 24 105

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