Stub minimization for assemblies without wirebonds to package substrate
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United States of America Patent
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Jan 14, 2014
Grant Date -
Apr 4, 2013
app pub date -
Apr 4, 2012
filing date -
Oct 3, 2011
priority date (Note) -
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Abstract
A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.
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