Alternating Wordline Connection in 8T Cells for Improving Resiliency to Multi-Bit SER Upsets
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United States of America Patent
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Issued Date -
Apr 4, 2013
app pub date -
Sep 29, 2011
filing date -
Sep 29, 2011
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Abandoned
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Abstract
An integrated circuit memory is disclosed in which an array of 8 T SRAM cells is arranged in rows and columns using a plurality of write wordlines for each row of 8 T SRAM cells to control write access to cells in the row associated with a first parity/ECC word and a second write wordline operable to control write access to cells in the row associated with a second parity/ECC word.
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