Serially connected memory having subdivided data interface
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United States of America Patent
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Apr 14, 2015
Grant Date -
Apr 4, 2013
app pub date -
Apr 26, 2011
filing date -
Apr 26, 2010
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Abstract
A memory system has a controller. A plurality of memory devices are serially interconnected with the controller via an n-bit data interface. The memory system is configurable in a first mode to communicate each read and write operation between the controller and the memory devices using all n bits of the data interface. The memory system is configurable in a second mode to concurrently: communicate data associated with a first operation between the controller and a first target memory device using only m bits of the data interface, where m is less than n; and communicate data associated with a second operation between the controller and a second target memory device using the remaining n-m bits of the data interface. A memory device, a memory controller, and a method are also described.
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