Frequency synthesis methods and systems

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United States of America Patent

PATENT NO 8756451
APP PUB NO 20130086410A1
SERIAL NO

13251220

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Abstract

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Multi-tier methods and systems to synthesize a reference frequency, and control one or more tiers in view of multiple prioritized criteria. A first tier of a frequency synthesizer may include a first phase locked loop (PLL), which may include an inductive-capacitive voltage-controlled oscillator (LC VCO). One or more subsequent tiers may each include a second PLL, which may include a self-biased (SB) VCO PLL or a digitally-controlled oscillator (DCO) PPL. A subsequent tier may be controllable with respect to multiple parameters. Parameters may be evaluated and selected based on multiple criteria, which may be prioritized. Parameters may be selected, for example, to minimize a frequency error equal relative to a permissible deviation from a desired frequency as a first priority, reduce jitter as a second priority, and minimize a frequency error relative to the desired frequency as a third priority.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Greiner, Robert J Beaverton, US 43 812
Grossnickle, Vaughn J Beaverton, US 12 120
Kurd, Nasser A Portland, US 63 837
Neidengard, Mark L Beaverton, US 11 103

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