Sharing a check bit memory device between groups of memory devices
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United States of America Patent
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Sep 22, 2015
Grant Date -
Apr 4, 2013
app pub date -
Sep 11, 2012
filing date -
Sep 30, 2011
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Abstract
A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.
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