Wafer level packaging using a lead-frame
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United States of America Patent
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Jul 22, 2014
Grant Date -
Apr 11, 2013
app pub date -
Jan 9, 2012
filing date -
Oct 10, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
Wafer level packaging using a lead-frame. When used to package two or more chips, a final product having QFN package-like finish. The final product will also have a performance rivaling or exceeding that of a corresponding monolithic chip because of the very close connection of the two or more chips and the ability to tailor the fabrication processing of each chip to only that required for the devices on that chip. The wafer level packaging can also be used to package monolithic chips, as well as chips having active devices on one chip and passive devices on a second chip. Various exemplary embodiments are disclosed.
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