Semiconductor memory device
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United States of America Patent
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Aug 12, 2014
Grant Date -
Apr 18, 2013
app pub date -
Apr 27, 2012
filing date -
Oct 18, 2011
priority date (Note) -
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Abstract
At least one of a plurality of columns is an LM column for storing LM flag data indicating a progression state of a write operation. Each of column control circuits performs an LM address scan operation for confirming whether the LM column exists in a corresponding memory core or not. Each of the column control circuits stores a result of that LM address scan operation in a register. In various kinds of operations after the LM address scan operation, each of the column control circuits executes an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is first data, and omits executing an operation of reading the LM flag data from the LM column in the corresponding one of the memory cores when data retained in the register is second data.
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