Parallel processing of network packets
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United States of America Patent
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Jul 15, 2014
Grant Date -
Apr 18, 2013
app pub date -
Oct 17, 2011
filing date -
Oct 17, 2011
priority date (Note) -
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Abstract
A packet processing circuit includes a plurality of header extraction circuits, and a scheduling circuit coupled to the plurality of header extraction circuits. The scheduling circuit is configured to receive one or more requests to extract header data of a respective packet from a data bus having a plurality of data lanes. In response to each request, the scheduling circuit determines a first subset of the plurality of data lanes that contain the respective header specified by the request, and assigns a respective one of the plurality of header extraction circuits to extract respective header data from the first subset of the plurality of data lanes.
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