TECHNIQUE FOR REDUCING TOPOGRAPHY-RELATED IRREGULARITIES DURING THE PATTERNING OF A DIELECTRIC MATERIAL IN A CONTACT LEVEL OF CLOSELY SPACED TRANSISTORS
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United States of America Patent
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Nov 20, 2012
filing date -
Apr 30, 2008
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Abstract
In a dual stress liner approach, the surface conditions after the patterning of a first stress-inducing layer may be enhanced by appropriately designing an etch sequence for substantially completely removing an etch stop material, which may be used for the patterning of the second stress-inducing dielectric material, while, in other cases, the etch stop material may be selectively formed after the patterning of the first stress-inducing dielectric material. Hence, the dual stress liner approach may be efficiently applied to semiconductor devices of the 45 nm technology and beyond.
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