Multi-core processor system, cache coherency control method, and computer product
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United States of America Patent
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Mar 31, 2015
Grant Date -
Apr 18, 2013
app pub date -
Dec 12, 2012
filing date -
Jun 14, 2010
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Abstract
A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
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