Stacked IC Devices Comprising a Workpiece Solder Connected to the TSV
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United States of America Patent
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Issued Date -
Apr 25, 2013
app pub date -
Apr 10, 2012
filing date -
Oct 16, 2008
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
A stacked integrated circuit (IC) device with at least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
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