Clock distribution circuit and method of forming clock distribution circuit

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United States of America Patent

PATENT NO 8736339
APP PUB NO 20130099844A1
SERIAL NO

13603755

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Abstract

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This invention includes a clock tree to which clock signals are distributed, and a phase comparison circuit configured to detect the phase difference between a plurality of feedback clock signals upon receiving the plurality of feedback clock signals output from different branching points of the clock tree. The invention includes a feedback clock signal generation circuit configured to generate a variation-corrected feedback clock signal for correcting a manufacture variation in the semiconductor integrated circuit based on the phase difference detected by the phase comparison circuit. The invention includes a phase regulation circuit configured to delay the clock signal so as to reduce the phase difference between a reference clock signal and the variation-corrected feedback clock signal generated by the feedback clock signal generation circuit.

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Patent Owner(s)

Patent OwnerAddress
CANON KABUSHIKI KAISHATOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kawaoka, Shigeo Tokyo, JP 3 8

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