Performing error detection on DRAMs

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 8811065
APP PUB NO 20130100746A1
SERIAL NO

13620565

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Abstract

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Large capacity memory systems are constructed using multiple groups of memory integrated circuits or chips. The memory system includes one or more interface circuits for interfacing between the multiple groups of memory integrated circuits and a memory controller. The interface circuit may detect and/or recover failed data using error-checking information stored in a memory integrated circuit.

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Patent Owner(s)

Patent OwnerAddress
GOOGLE LLC1600 AMPHITHEATRE PARKWAY MOUNTAIN VIEW CA 94043

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Rajan, Suresh Natarajan San Jose, US 80 11498
Smith, Michael John Sebastian Palo Alto, US 79 10889
Wang, David T Thousand Oaks, US 97 11981

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