Multi-processor architecture using multiple switch fabrics implementing point-to-point serial links and method of operating same
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United States of America Patent
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Oct 7, 2014
Grant Date -
Apr 25, 2013
app pub date -
Dec 14, 2012
filing date -
Jul 10, 2009
priority date (Note) -
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Abstract
A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards.
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