Memory controller, semiconductor memory system, and memory control method
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United States of America Patent
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Sep 2, 2014
Grant Date -
Apr 25, 2013
app pub date -
Aug 24, 2012
filing date -
Oct 19, 2011
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Abstract
According to one embodiment, a memory controller that controls a non-volatile semiconductor memory including a memory cell of 3 bits/cell includes a controller that extracts bits which becomes an error caused by the movement to the adjacent threshold voltage distribution from a first bit and a second bit of data to be written in each of the memory cells to generate a virtual page and an encoding unit that generate an error correcting code for the virtual page and writes the data for three pages and the error correcting code in the non-volatile semiconductor memory.
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