MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation
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United States of America Patent
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Nov 5, 2013
Grant Date -
May 2, 2013
app pub date -
Oct 27, 2011
filing date -
Oct 27, 2011
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Abstract
A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
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