Non-volatile memory devices having vertical drain to gate capacitive coupling

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United States of America Patent

PATENT NO 9230814
APP PUB NO 20130107630A1
SERIAL NO

13284783

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Abstract

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Vertically fabricated non-volatile memory devices having capacitive coupling between a drain region and a floating gate. A two terminal programmable non-volatile device includes a floating gate disposed vertically about a substrate, wherein the floating gate comprises a first side, a second side, and a bottom portion. A source region is coupled to a first terminal and formed adjacent to the first side of the floating gate. A drain region is coupled to a second terminal and formed adjacent to the second side of the floating gate. The non-volatile device includes a channel coupling the source region and drain region for programming and erasing operations. The drain region is capacitively coupled to the floating gate.

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Patent Owner(s)

Patent OwnerAddress
ADEIA SEMICONDUCTOR TECHNOLOGIES LLC3025 ORCHARD PARKWAY SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fisch, David Edward Pleasanton, US 28 690
Parris, Michael Curtis San Jose, US 6 26

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