Clock drift compensation interpolator adjusting buffer read and write clocks
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United States of America Patent
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Apr 21, 2015
Grant Date -
May 2, 2013
app pub date -
Nov 9, 2011
filing date -
Oct 31, 2011
priority date (Note) -
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Abstract
In at least some embodiments, an electronic device includes a data sink and a buffer coupled to the data sink. The buffer is configured to receive streaming data in transit to the data sink. The electronic device also includes a clock drift compensation controller coupled to the buffer, wherein the clock drift compensation controller is configured to apply either of two predetermined clock drift compensation values to a clock rate for the buffer whenever a buffer fullness status value is offset from a predetermined threshold.
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