Dynamically controlling cache size to maximize energy efficiency

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United States of America Patent

PATENT NO 9158693
SERIAL NO

13285465

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Abstract

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In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abu-Salah, Hisham Majdal Shams, IL 13 242
Ananthakrishnan, Avinash N Hillsboro, US 77 1610
Naveh, Alon Ramat Hasharon, IL 115 2809
Rajwan, Doron Rishon Le-Zion, IL 123 2139
Rotem, Efraim Haifa, IL 204 3587
Shulman, Nadav Tel Mond, IL 76 1153
Weissmann, Eliezer Haifa, IL 190 2397

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