Multi-core processor system, control program, and control method
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United States of America Patent
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Jun 9, 2015
Grant Date -
May 2, 2013
app pub date -
Dec 19, 2012
filing date -
Jun 22, 2010
priority date (Note) -
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Abstract
A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
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