Memory controller with staggered request signal output
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United States of America Patent
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Jan 28, 2014
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N/A
app pub date -
Dec 19, 2012
filing date -
Oct 17, 2005
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Abstract
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
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