Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions
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United States of America Patent
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Nov 18, 2014
Issued Date -
N/A
app pub date -
Nov 2, 2011
filing date -
Nov 2, 2011
priority date (Note) -
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Abstract
A circuit arrangement and method support compression and expansion of instruction opcodes by detecting successive address targeting and decoding a first opcode of an instruction into a second opcode in response to detecting successive address targeting. The circuit arrangement and method execute instructions in an instruction stream and detect successive address targeting by two or more instructions in the instruction stream without the targeted address being utilized as a source address in an instruction executed between the first and second instructions in the instruction stream. Then, based on that detection, the opcode of the second instruction is modified, changed, or appended to such that a different opcode is indicated by the second instruction, such that executing the second instruction causes a different unique type of operation to be performed.
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