THROUGH SILICON VIA FOR STACKED WAFER CONNECTIONS
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United States of America Patent
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Issued Date -
May 16, 2013
app pub date -
Nov 16, 2011
filing date -
Nov 16, 2011
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
Stacked wafer connections are enhanced by forming a though silicon via including a first via portion formed in an upper portion of a via hole and a second via portion in a lower portion of the via hole. Embodiments include forming a via hole in a first surface of a substrate; partially filling the via hole with a dielectric material; filling the remainder of the via hole with a first conductive material; removing a portion of a second surface of the substrate to expose the dielectric material; removing the dielectric material from the via hole; and filling a the via hole with a second conductive material electrically conductively connected to the first conductive material.
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