Agile clocking with receiver PLL management
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United States of America Patent
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Feb 4, 2014
Grant Date -
May 16, 2013
app pub date -
Mar 30, 2012
filing date -
Nov 14, 2011
priority date (Note) -
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Abstract
A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.
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