Delay-locked-loop circuit
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United States of America Patent
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Mar 18, 2014
Grant Date -
May 16, 2013
app pub date -
Dec 28, 2012
filing date -
Jan 5, 2010
priority date (Note) -
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Abstract
A delay-locked-loop (DLL) circuit having a DLL that operates when an external clock signal has a low frequency and a DLL that operates when an external clock signal has a high frequency is disclosed. The DLL circuit includes a first DLL and second DLL. The first DLL adjusts a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency. The second DLL adjusts the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.
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