System with controller and memory
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United States of America Patent
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Feb 4, 2014
Grant Date -
May 16, 2013
app pub date -
Jan 8, 2013
filing date -
Jun 8, 2006
priority date (Note) -
In Force
status (Latency Note)
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Abstract
According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.
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