Anneal to minimize leakage current in DRAM capacitor
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United States of America Patent
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Feb 11, 2014
Grant Date -
May 16, 2013
app pub date -
Nov 14, 2011
filing date -
Nov 14, 2011
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Abstract
A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen.
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