Blocking layers for leakage current reduction in DRAM devices
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United States of America Patent
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Nov 5, 2013
Grant Date -
May 16, 2013
app pub date -
Jan 10, 2013
filing date -
Nov 7, 2011
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Abstract
A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.
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