N/P boundary effect reduction for metal gate transistors
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United States of America Patent
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Apr 22, 2014
Grant Date -
May 23, 2013
app pub date -
Nov 17, 2011
filing date -
Nov 17, 2011
priority date (Note) -
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Abstract
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.
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