Integrated circuits with electrical fuses and methods of forming the same
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United States of America Patent
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Dec 20, 2016
Grant Date -
May 23, 2013
app pub date -
Nov 22, 2011
filing date -
Nov 22, 2011
priority date (Note) -
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Abstract
A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
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