(110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate

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United States of America Patent

PATENT NO 9406518
APP PUB NO 20130126985A1
SERIAL NO

13299529

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Abstract

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A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Chao-Ching Hsinchu, TW 148 545
Ko, Chih-Hsin Fongshan, TW 216 11072
Wann, Hsingjen Carmel, US 12 189

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