Reduced susceptibility to electrostatic discharge during 3D semiconductor device bonding and assembly
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United States of America Patent
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Dec 10, 2013
Grant Date -
May 23, 2013
app pub date -
May 14, 2012
filing date -
Apr 9, 2009
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Abstract
Electrostatic discharge susceptibility is reduced when assembling a stacked IC device by coupling a ground plane of a first semiconductor device and a ground plane of a second semiconductor device to place the ground plane at substantially a same electrical potential. Active circuitry on the first semiconductor device and active circuitry on the second semiconductor device are electrically coupled after the ground planes are coupled. Electrically coupling the ground planes of the first and the second semiconductor device creates a preferred electrostatic discharge path to ground, thus reducing potential damage to sensitive circuit elements.
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