CMOS image sensor big via bonding pad application for AICu process
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United States of America Patent
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Mar 25, 2014
Grant Date -
May 30, 2013
app pub date -
Dec 27, 2012
filing date -
Jul 29, 2009
priority date (Note) -
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Abstract
An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.
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