Chip-on-Wafer structures and methods for forming the same
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United States of America Patent
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Feb 4, 2014
Grant Date -
May 30, 2013
app pub date -
Feb 15, 2012
filing date -
Nov 30, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level.
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