Planarized bumps for underfill control
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United States of America Patent
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Feb 18, 2014
Issued Date -
N/A
app pub date -
Nov 30, 2011
filing date -
Nov 30, 2011
priority date (Note) -
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Abstract
The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved.
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