Dual rail memory architecture
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United States of America Patent
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Apr 28, 2015
Grant Date -
May 30, 2013
app pub date -
Jul 17, 2012
filing date -
Nov 30, 2011
priority date (Note) -
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Abstract
A memory macro comprises a plurality of memory cells, a plurality of first amplifying circuits, a first driver circuit, and a first level shifter. The plurality of memory cells is arranged in groups of a first direction and groups of a second direction. Each amplifying circuit is coupled to a plurality of first memory cells arranged in a first group of the first direction via a first data line. The first driver circuit is configured to drive the plurality of first amplifying circuits. The first level shifter is configured to level shift an input signal operating in a first power domain to an output signal operating in a second power domain. The output signal of the first level shifter is for use by the first driver circuit. The first driver circuit and a sense amplifier of an amplifying circuit operate in the second power domain.
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