Metal gate features of semiconductor die
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United States of America Patent
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Apr 14, 2015
Grant Date -
Jun 6, 2013
app pub date -
Dec 6, 2011
filing date -
Dec 6, 2011
priority date (Note) -
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Abstract
A CMOS semiconductor die comprises a substrate; an insulation layer over a major surface of the substrate; a plurality of P-metal gate areas formed within the insulation layer collectively covering a first area of the major surface; a plurality of N-metal gate areas formed within the insulation layer collectively covering a second area of the major surface, wherein a first ratio of the first area to the second area is equal to or greater than 1; a plurality of dummy P-metal gate areas formed within the insulation layer collectively covering a third area of the major surface; and a plurality of dummy N-metal gate areas formed within the insulation layer collectively covering a fourth area of the major surface, wherein a second ratio of the third area to the fourth area is substantially equal to the first ratio.
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