Integrated circuit having stress tuning layer
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United States of America Patent
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Mar 1, 2016
Issued Date -
N/A
app pub date -
Dec 28, 2012
filing date -
May 16, 2006
priority date (Note) -
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Abstract
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.
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