Processor-bus-connected flash storage paging device using a virtual memory mapping table and page faults
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United States of America Patent
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Jan 7, 2014
Grant Date -
Jun 6, 2013
app pub date -
Dec 31, 2012
filing date -
Oct 1, 2009
priority date (Note) -
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Abstract
A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address.
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