Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits
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United States of America Patent
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Oct 28, 2014
Grant Date -
Jun 13, 2013
app pub date -
Dec 12, 2011
filing date -
Dec 12, 2011
priority date (Note) -
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Abstract
An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
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