Passivation layer for packaged chip
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United States of America Patent
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Oct 15, 2013
Grant Date -
Jun 13, 2013
app pub date -
Dec 7, 2011
filing date -
Dec 7, 2011
priority date (Note) -
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Abstract
The embodiments described above provide mechanisms for forming metal bumps on metal pads with testing pads on a packaged integrated circuit (IC) chip. A passivation layer is formed to cover the testing pads and possibly portions of metal pads. The passivation layer does not cover surfaces away from the testing pad region and the metal pad region. The limited covering of the testing pads and the portions of the metal pads by the passivation layer reduces interface resistance for a UBM layer formed between the metal pads and the metal bumps. Such reduction of interface resistance leads to the reduction of resistance of the metal bumps.
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