Post-passivation interconnect structure
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United States of America Patent
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Apr 4, 2017
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N/A
app pub date -
Dec 7, 2011
filing date -
Dec 7, 2011
priority date (Note) -
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Abstract
A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.
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