Control scheme for 3D memory IC
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United States of America Patent
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Apr 21, 2015
Grant Date -
Jun 13, 2013
app pub date -
Jun 15, 2012
filing date -
Dec 13, 2011
priority date (Note) -
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Abstract
The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.
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