Semiconductor memory device and method of performing burn-in test on the same
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United States of America Patent
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Jul 15, 2014
Grant Date -
Jun 13, 2013
app pub date -
Oct 17, 2012
filing date -
Dec 8, 2011
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Abstract
A semiconductor memory device includes a cell array having a plurality of memory cells, each memory cell including a resistive element and a cell transistor between a bit line and a source line, and a source line voltage supply unit configured to supply, in a normal mode, a reference source line voltage to the source line, and in a test mode, a first source line voltage to the source line when data in a first state is recorded and a second source line voltage to the source line when data in a second state is recorded, the first source line voltage being lower than the reference source line voltage, and the second source line voltage being higher than the reference source line voltage.
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